1. Field of the Invention
The present invention relates to integrated circuits, and more particularly to output buffers of integrated circuits.
2. Description of the Related Art
Devices producing clocks for use in a system may communicate with a variety of types of input buffers, each type having its own impedance, signal swing, and common mode requirements. Traditionally, clock source integrated circuits produce outputs which have a predetermined signal format, thus integrated circuit designers have used various techniques to provide an interface between the input and output buffers having different signal formats.
For example, an integrated circuit may provide multiple output signal formats by including duplicate output bond pads. Each bond pad (or pair of pads for differential formats) has a corresponding output buffer circuit. During a packaging process, the desired pads are bonded to package pins and the unconnected pads and buffer are unused. While this approach allows one integrated circuit to generate multiple signal formats, extra area is consumed by the unused buffer and pads, and the signal format must be selected during the packaging process.
Another technique for providing an interface between input and output buffers having different signal formats includes designing separate integrated circuits for each output signal format to avoid wasting die area of unused buffer(s). This approach introduces additional mask costs if the designs are processed on separate mask sets. Like the former technique, the signal format must be selected during the packaging process. Both of the former and latter techniques require additional inventory because stock must be kept for each part number.
Conversion buffers may be used to provide an interface between input and output buffers having different signal formats. This approach allows one integrated circuit to be used in multiple applications requiring different numbers and types of loads. However, conversion buffers introduce the costs of additional board space and additional clock jitter. For high precision applications, the buffer jitter can significantly degrade system performance.
Accordingly, improved techniques for communicating between an output buffer and an input buffer having different signal formats are desired.